The present invention relates to a nonvolatile semiconductor storage device of a virtual ground system and a read method for the nonvolatile semiconductor storage device.
There has conventionally been known a semiconductor storage device intended for preventing the flow of a current from a word line to a bit line and a virtual GND line (Japanese Patent Laid-Open Publication No. HEI 6-68683). In this semiconductor storage device, as shown in FIG. 7, memory cell transistors are connected in an array form to bit lines 1 through 4 and virtual GND lines 5 through 9. Moreover, metal bit lines 10 through 12 are provided commonly for two bit lines of each block constructed of two bit lines (bit lines 2 and 3, for example). A precharge circuit 17, which has transistors 14 through 16 connected to the metal bit lines 10 through 12, respectively, is arranged between a Y gate 13 and the memory cell array.
Metal virtual GND lines 18 and 19 are provided one per block constructed of adjoining two virtual GND lines (virtual GND lines 6 and 7, for example). The metal virtual GND lines 18 and 19 are connected to precharge select circuits 20 and 21, respectively. It is to be noted that reference numerals 22 and 23 denote bit line select lines, numerals 24 and 25 denote virtual GND line select lines, and a numeral 26 denotes a word line.
When, for example, a memory cell transistor 27 is read in the semiconductor storage device that has the aforementioned construction, the voltages of the word line 26, the virtual GND line select line 24 and the bit line select line 22 are pulled up to a Vcc level. The voltages of the virtual GND line select line 25 and the bit line select line 23 are pulled down to the GND level. In the above case, only the voltage of the metal virtual GND line 18 is pulled down to the GND level by the precharge select circuit 20, while the voltages of all the other virtual GND lines 19 are set to a precharge level by the precharge select circuit 21. By this operation, only the voltages of the two virtual GND lines 6 and 7 that constitute one block come to have the GND level, while the voltages of other virtual GND lines 5, 8 and 9 come to have the precharge level. Moreover, the metal bit line 11 is selected by a Y gate 13. In the above case, the voltage of the bit line select line 22 has the Vcc level, and the bit line select line 23 has the GND level, as described above. Consequently, a transistor 28 is turned OFF, and a transistor 29 is turned ON. Therefore, the bit line 3 is connected to the metal bit line 11 via the transistor 29 so as to be put in a selected state. By this operation, the memory cell transistor 27 is brought into the selected state.
There is another semiconductor storage device as shown in FIG. 8, in which the current from the word line is prevented from flowing into the bit line and the virtual GND line (Japanese Patent Laid-Open Publication No. HEI 10-11991). As shown in FIG. 8, this semiconductor storage device is constituted roughly of a NOR type cell array constructed of memory cell transistors M01 through Mn8, a select circuit 31, a precharge circuit 32, a sense amplifier 33, a select circuit 34, a precharge circuit 35 and so on. There are further provided bit lines and virtual GND lines D1 through D9, word lines WD0 through WDn, bit-line select transistors S1 through S6, virtual GND line select transistors S11 through S17, bit line select lines BS0 and BS1 and virtual GND line select lines BS2 and BS3.
Furthermore, bit line select circuits SEL1 and SEL2, which are respectively constructed of three bit line select transistors S1 through S3 and S4 through S6, are connected to memory cell transistors M arranged in four columns and select the bit lines and virtual GND lines D in units of columns. Among the bit line select transistors S1, S2 and S3 that constitute the bit line select circuit SEL1, the bit line select transistors S1 and S3 have their gates commonly connected to a bit line select line BS0, have their sources connected to a select circuit 31 via a bit line Y1 and have their drains connected to the bit lines and virtual GND lines D2 and D4. The bit line select transistor S2 has its gate connected to a bit line select line BS1, has its source connected to a select circuit 31 via a bit line Y1 and has its drain connected to the bit line and virtual GND line D3.
When, for example, the memory cell transistor M01 is read in the semiconductor storage device having the aforementioned construction, the voltages of the word line WD0 connected to the gate of the memory cell transistor M01, the bit line select line BS0 connected to the gate of the bit line select transistor S1 whose drain is connected to the drain (or source) of the memory cell transistor M01 and the virtual GND line select line BS3 connected to the gate of the virtual GND line select transistor S11 whose drain is connected to the source (or drain) of the memory cell transistor M01 are pulled up to the VCC level, turning ON the bit line select transistor S1 and the virtual GND line select transistor S11.
At the same time, the voltages of the bit line select line BS1 and the virtual GND line select line BS2 are pulled down to the GND level, turning OFF the bit line select transistors S2 and S5 and the virtual GND line select transistors S12, S13, S15 and S16. The select circuit 31 connects the bit line Y1 to the sense amplifier 33 and connects the bit line Y2 to the precharge circuit 32. Furthermore, the select circuit 34 connects a virtual GND line VG1 to the virtual GND and connects the virtual GND lines VG2 and VG3 to the precharge circuit 35.
Therefore, the bit line Y1 and the bit line and virtual GND line D2 are connected together by the bit line select transistor S1 turned ON. The virtual GND line VG1 and the bit line and virtual GND line D1 are connected together by the virtual GND line select transistor S11 turned ON. As a result, among the bit line and virtual GND lines D1 and D2, the line xe2x80x9cD2xe2x80x9d becomes the bit line, and the line xe2x80x9cD1xe2x80x9d becomes the virtual GND line, bringing the memory cell transistor M01 into the selected state.
However, the conventional semiconductor storage device of the virtual GND system has the problem that misread will possibly occur due to a leak current from the memory cell transistors 30 and M04, which share the word lines WL and WD0 with the memory cell transistors 27 and M01.
First of all, in the case of the aforementioned semiconductor storage device of Japanese Patent Laid-Open Publication No. HEI 6-68683, when the memory cell transistor 27 is selected in FIG. 7, the voltage of the virtual GND line 8 is also pulled up to the precharge level Vpc since the virtual GND line select line 24 has the voltage level of Vcc. Therefore, when the memory cell transistor 30 is ON, a superfluous current flows into the metal bit line 11 through the memory cell transistor 30, as a consequence of which the reduction in the potential of the metal bit line 11 is hindered when the memory cell transistor 27 is ON, possibly causing an operation as if the memory cell transistor 27 were an OFF cell.
Next, in the case of the aforementioned semiconductor storage device of Japanese Patent Laid-Open Publication No. HEI 10-11991, when the memory cell transistor M01 is selected in FIG. 8, the bit line select transistor S3 is also turned ON concurrently with the turning-on of the bit line select transistor S1. In this case, when the memory cell transistor M04 connected to the selected word line WD0 is ON, a current flows into the bit line Y1 via the memory cell transistor M04 and the bit line select transistor S3 since the non-selected bit line D5 has the precharge level, as a consequence of which the reduction in the potential of the bit line Y1 is prevented when the memory cell transistor M01 is ON, possibly causing an operation as if the memory cell transistor M01 were an OFF cell.
Accordingly, the object of the present invention is to provide a nonvolatile semiconductor storage device of the virtual ground system in which the selected memory cell can correctly be read even when the threshold value of the non-selected memory cell that shares a word line WL with this selected memory cell is low and a read method therefor.
In order to achieve the aforementioned object, there is provided a nonvolatile semiconductor storage device having a plurality of nonvolatile memory cells arranged in a matrix form and bit lines and word lines connected to the nonvolatile memory cells, the nonvolatile memory cells adjoining in a direction in which the word lines extend sharing one bit line, the device comprising:
a full bit precharge means for charging all the bit lines with electric charges;
a selective discharge means for selectively discharging one or more adjoining bit lines that include either one of two bit lines connected to a selected nonvolatile memory cell;
a selective precharge means for selectively applying a precharge voltage to any one of one or more bit lines adjacent to the other bit line of the two bit lines connected to the selected nonvolatile memory cell;
a precharge control circuit for operating the full bit precharge means during full bit precharge for charging all the bit lines and operating the selective precharge means in a read operation; and
a discharge control circuit for operating the selective discharge means in the read operation.
According to the above-mentioned construction, when reading the stored information of the selected memory cell, the full bit precharge means is first operated by the precharge control circuit so as to charge the full bit line. All the bit lines are brought into the floating state in the above state, and thereafter, the selective discharge means is operated by the discharge control circuit so as to selectively discharge one or more adjoining bit lines that include either one bit line of the two bit lines connected to the selected memory cell. Furthermore, the selective precharge means is operated by the precharge control circuit so as to selectively apply the precharge voltage to any one of the one or more bit lines adjacent to the other bit lines.
By the above operation, the current leak via the non-selected memory cell from the drain of the selected memory cell is prevented even when the threshold value of the selected memory cell is high and the threshold value of the non-selected memory cell is low, and the potential of the drain is kept at the precharge potential. Thus, correct read is executed. When the threshold value of the selected memory cell is low and the threshold value of the non-selected memory cell is low, the drain of the selected memory cell is charged with electric charges from the selectively precharged bit line. However, before receiving the influence of the charges, the precharge potential of the other bit line is pulled down to one-third, for example, by the bit line located on the one discharged side. Thus, the correct read is executed.
That is, no misread occurs since the other bit line is provided with a sufficient potential difference between the potential when the threshold value of the selected memory cell is high and the potential when the threshold value is low even if the sense timing of the other bit line connected to the selected memory cell is delayed for some reasons.
In one embodiment, the bit line to which the precharge voltage is applied by the selective precharge means is one bit line located at a center of the plurality of adjoining bit lines that include the other bit line.
According to the above-mentioned construction, the drain potential when the threshold value of the selected memory cell is high does not receive the influence of the current leak occurring from the precharge voltage applied bit line toward the discharged bit line via the non-selected memory cell, dissimilar to the case where the bit line to which the precharge voltage is applied is positioned on the opposite side of the selected memory cell with respect to the center of the plurality of adjoining bit lines that include the other bit line. The drain voltage when the threshold value of the selected memory cell is low does not receive the influence of the electric charges occurring from the precharge voltage applied bit line via the non-selected memory cell, dissimilar to the case where the precharge voltage applied bit line is positioned on the selected memory cell side with respect to the center.
In one embodiment, the bit lines, which are selectively discharged by the selective discharge means, are three bit lines, and
the plurality of bit lines, where the bit line to which the precharge voltage is applied by the selective precharge means is located at the center, are five bit lines.
In one embodiment, each of the full bit precharge means, the selective precharge means and the selective discharge means is constituted of a plurality of transistors whose sources or drains are connected to the bit lines,
the precharge control circuit supplies a control signal to gates of the transistors that constitute the full bit precharge means and the selective precharge means, and
the discharge control circuit supplies a control signal to gates of the transistors that constitute the selective discharge means.
According to the above-mentioned construction, the full bit precharge means, the selective precharge means and the selective discharge means are constituted by arranging same transistors in a line. Therefore, the area occupied by the above-mentioned means is reduced. Furthermore, the selective discharge of the bit line and the selective application of the precharge voltage are executed in units of individual bit lines. Therefore, the number of the discharged bit lines, the number of the non-discharged bit lines and the position of the precharge voltage applied bit line can easily be changed only by changing the precharge control circuit or the discharge control circuit.
There is provided a method for reading a nonvolatile semiconductor storage device having a plurality of nonvolatile memory cells arranged in a matrix form and bit lines and word lines connected to the nonvolatile memory cells, the nonvolatile memory cells adjoining in a direction in which the word lines extend sharing one bit line, the method comprising the steps of:
precharging all the bit lines with electric charges;
activating a word line connected to a selected nonvolatile memory cell;
selectively discharging one or more adjoining bit lines that include either one of two bit lines connected to the selected nonvolatile memory cell;
selectively applying a precharge voltage to one bit line that is located at a center of a plurality of adjoining bit lines that include the other bit line of the two bit lines connected to the selected nonvolatile memory cell; and
reading information stored in the selected nonvolatile memory cell from the other bit line.
According to the above-mentioned construction, similarly to the case of the first inventive aspect, when the threshold value of the selected memory cell is high and the threshold value of the non-selected memory cell is low, the current leak occurring from the drain of the selected memory cell via the non-selected memory cell is prevented since the precharge voltage is applied to the one bit line located at the center of the non-discharged bit lines, and the potential of the drain is kept at the precharge potential. Thus, the correct read is executed. When the threshold value of the selected memory cell is low and the threshold value of the non-selected memory cell is low, the precharge potential of the other bit line is pulled down by the discharged one bit line before the drain potential of the selected memory cell receives the influence of the electric charges from the precharge voltage applied bit line. Thus, the correct read is executed.